1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a buried contact (AC).
2. Description of the Related Art
In the current art, a polysilicon layer makes contact with a single crystal silicon substrate via a buried contact as integration of a semiconductor device increases. However, the conventional method of forming the buried contact causes some drawbacks.
FIGS. 1A through 1D are schematic, cross-sectional views showing the progression of conventional manufacturing steps for a buried contact.
As shown in Fig. 1A, a gate oxide layer 104 and a polysilicon layer 106 are formed in sequence on a substrate 100 having an insulating region 102 formed therein. A photoresist layer 108 for forming a buried contact is formed on the polysilicon layer 106; the polysilicon layer 106 and the gate oxide layer 104 are patterned to expose the substrate 100 by plasma etching. Then, an ion implantation step 109 is performed to form a buried contact 110 in the substrate 100.
As shown in Fig. 11B, the photoresist layer 108 is removed. A polysilicon layer 112 is formed over the substrate 100 and couples with the buried contact 110. Then, a photoresist layer 114 is formed on the polysilicon layer 112. Photoresist layer 114 is subsequently for defining a gate and a conductive wire coupled with the buried contact 110. An edge 134 of the photoresist layer 114 is precisely aligned over an edge 136 of the buried contact 110.
As shown in Fig. 1C, a portion of the polysilicon layer 112 and a portion of the polysilicon layer 106 are removed by a plasma etching process to form a gate 116 and a conductive wire 118 coupled with the buried contact 110; the gate oxide layer 104 serves as an etching stop layer during the plasma etching process. Furthermore, the gate oxide layer 104 also serves as a protective layer to protect the substrate 100 from damage during the plasma etching process. Next, an ion implantation step 120 is performed to form a lightly doped source/drain region (LDD) 122 in the substrate 100.
As shown in Fig. 1D, spacers 124 and 126 are formed on sidewalls of the gate 116 and sidewalls of the conductive wire 118, respectively. An ion implantation step 128 is then performed to form a heavily doped source/drain region 130 in the substrate 100 while using the gate 116, the spacer 124, the spacer 126 and the conductive wire 118 as a mask. The lightly doped source/drain region 122 and the heavily doped source/drain region 130 constitute a source/drain region 132, and the source/drain region 132 connects to the buried contact 110.
In the method mentioned above, the source/drain region 132 is electrically connected with the conductive wire 118 through the buried contact 110. To form this structure, the edge 134 of the photoresist layer 114 (FIG. 1B) must be precisely aligned over the edge 136 of the buried contact 110 (Fig. 1B). Once misalignment occurs, electrical discontinuity between the buried contact 110 and the source/drain region 132 occurs.
The following shows the problems caused by misalignment. FIGS. 2A through 2B are schematic, cross-sectional views of what happens due to a positive offset while aligning the edge of the photoresist layer over the edge of the buried contact. FIGS. 3A through 3B are schematic, cross-sectional views of what happens due to a negative offset while aligning the edge of the photoresist layer over the edge of the buried contact.
As shown in FIG. 2A, during the process of forming the gate 116 and the conductive wire 118, an edge 134a of the photoresist layer 114 is located in a range 142 due to a positive offset, i.e., misalignment occurs. Thus, a portion of the polysilicon layer 112 on the buried contact 110 is exposed. Since no gate oxide layer 104 exists between the portion of the polysilicon layer 112 on the buried contact 110 and the substrate 100, a micro-trench 140, as illustrated in FIG. 2B, is easily formed within the buried contact 110 while performing the plasma etching process, and the subsequently formed spacer 126 fills the micro-trench 140. Electrical continuity between the buried contact 110 and the source/drain region 132 is affected by the spacer 126 in the micro-trench 140. In particular, when the micro-trench 140 is deeper than the buried contact 110 as shown in FIG. 2B, the source/drain region 132 cannot electrically couple with the buried contact 110, so the buried contact 110 fails.
Referring to FIG. 3A, a position of an edge 134b of the photoresist layer 114 exceeds the range 142 because of a negative offset. After the gate 116 and the conductive wire 118 are formed, the conductive wire 118 not only covers the buried contact 110, but also covers a portion of the substrate 100. As a result, the source/drain region 132 formed while using the gate 116, the spacer 124, the spacer 126 and the conductive wire 118 as a mask is not adjacent to the buried contact 110 as shown in FIG. 3B. Electrical dis-continuity between the buried contact 110 and the source/drain region 132 occurs, so the buried contact 110 fails.
According to the above statements, some disadvantages are caused by misalignment in the process for forming the buried contact. Because of a positive offset, a micro-trench is easily formed within the buried contact and the source/drain region therefore cannot couple with the buried contact. Due to a negative offset, the source/drain region is not formed adjacent to the buried contact, and thus electrical discontinuity between the buried contact and the source/drain region occurs. Although these disadvantages can be overcome by optimizing the process, the method of optimizing the process reduces the process window. As a result, the process becomes difficult and throughput of the process is also decreased.